1. Field of the Invention
The invention relates to the structure and fabrication of integrated circuits, particularly those which utilize ferroelectric and/or high dielectric constant thin films.
2. Statement of the Problem
As is well-known, integrated circuits (ICs) are fabricated by layering and patterning thin films on a substrate, such as a thin slice of a single crystal of silicon or gallium arsenide. The patterning process is a complicated and expensive one that normally requires the application of a photo resist layer, exposure of the resist through a mask to define the device pattern, etching to remove portions of the thin film materials, and removal of the remaining resist in a solvent wash.
It is also well-known that ferroelectric materials, particularly lead zirconium titanate (PZT) are useful in integrated circuits. See, for example, U.S. Pat. No. 5,046,043 issued Sep. 3, 1991 to William D. Miller et al. Recently, a new class of materials, called layered superlattice materials, have been found to be far superior to PZT for ferroelectric uses and U.S. Pat. No. 5,519,234 issued May 21, 1996 to Carlos A. Paz De Araujo et al. These materials are more complex than PZT; while PZT is a solid solution of two ABO.sub.3 type perovskites, layered superlattice materials are materials that spontaneously form complex crystal structures having collated intergrowth layers. Thus, they are more difficult to form than PZT and are more susceptible to damage by conventional integrated circuit processing.
It is known that some materials, such as PZT, may be self-patterned, thereby eliminating the need for some of the photo-resist and etching steps. See, Yuichi Nakao, et. al., Micro-Patterning of PbZr.sub.x T.sub.1-x O.sub.3 Thin Films Prepared by Photo Sensitive Sol-Gel Solutions, Jpn. J. Appl. Phs. Vol. 32, Part 1, No. 9B, pp. 4141-4143, September 1993 and Soyama et al., The Formation of a Fine-Patterned Ferroelectric Thin-Film From a Sol-Gel Solution Containing a Photo-Sensitive Water Generator, Proceedings Of The International Symposium On Applied Ferroelectrics (1994).
While the materials, structures, and processes discussed in the above references are significant advances, these advances have lead to serious new problems related to the integration of the ferroelectric materials, in particular the layered superlattice materials, and the self-patterning processes into conventional CMOS integrated circuit technology. See for example, H. Achard and H. Mace, "Integration of Ferroelectric Thin Films For Memory Applications", in O. Auciello and R. Waser (eds.), Science and Technology of Electroceramic Thin Films, pp. 353-372, 1995, Kiuwer Academic Publishers, Netherlands, which discusses the problem of etching a nonconformal coating deposited by the sol-gel method (pp. 358-360) for which there is no process window and the difficulties in the "back-end" stages of processing (p. 367). The conventional process in which the three layers of the ferroelectric capacitor are etched in a single mask and etch process has been found to result in leakage between the top and bottom electrodes of the capacitor. The conventional hydrogen forming gas reduction back-end process, which is essential to CMOS integrated circuits, has been found to be quite destructive of ferroelectric materials; particularly the layered superlattice materials. See for example, Takashi Hase, Takehiro Noguchi and Yoichi Miyasaka, "Analysis of the Degradation of PZT and SrBi.sub.2 Ta.sub.2 O.sub.9 Thin Films With A Reductive Process", in Abstracts of the 8th International Symposium on Integrated Ferroelectrics, Mar. 18-20, 1996, p. 11 c. A 1 transistor-1 capacitor ferroelectric memory cell structure having a ferroelectric capacitor in which the ferroelectric material covers one end of the bottom electrode and extends out beyond the top electrode at the other end to solve the leakage problem, and includes a titanium oxide (TiO.sub.2) reaction barrier layer overlying the ferroelectric capacitor to solve the problem of the reduction of the ferroelectric by the hydrogen forming gas has been attempted. See, Iisub Chung, Chang Jung Kim, Chee Won Chung, and In Keong Yoo, "Integration of Ferroelectric Capacitors Using Multilayered Electrode", in The Tenth International Symposium on the Applications of Ferroelectrics, Aug. 18-21, 1996, p.55. However, the titanium in this protective layer can itself lead to new problems in the integrated circuit. In addition, the proposed memory structure is relatively large, and thus does not lend itself to dense, economical integrated circuits. Thus, it would be highly desirable to have integrated circuit materials, structures, and processes that solve the capacitor leakage and back-end process problems, were compatible with important ferroelectric materials, permit the use of self-patterning materials in integrated circuits, and/or which result in a more dense memory cell structure and a more economical memory cell fabrication process.